module mode_decoder(
        input   [ 4:0]  i_mode,
        output          o_usrbank,
        output          o_fiqbank,
        output          o_irqbank,
        output          o_svcbank,
        output          o_abtbank,
        output          o_undbank
);

wire usrmode = ~i_mode[1] & ~i_mode[0];
wire fiqmode = ~i_mode[1] &  i_mode[0];
wire irqmode =  i_mode[1] & ~i_mode[0];
wire svcmode = ~i_mode[3] &  i_mode[1] &  i_mode[0];
wire abtmode = ~i_mode[3] &  i_mode[2];
wire undmode =  i_mode[3] & ~i_mode[2];
wire sysmode =  i_mode[3] &  i_mode[2];

assign o_usrbank = usrmode | sysmode ;
assign o_fiqbank = fiqmode ;
assign o_irqbank = irqmode ;
assign o_svcbank = svcmode ;
assign o_abtbank = abtmode ;
assign o_undbank = undmode ;

endmodule
